Summary
- SCI Semiconductor has raised £5 million after previously securing £2.5 million in investment.
- The company says it has more than £2 million in orders and £7.7 million in government contracts.
- Its ICENI chips use CHERI-derived technology intended to enforce memory protections in hardware.
Sheffield-based SCI Semiconductor has raised £5 million to increase production of its memory-safety chips, providing a commercial test for technology designed to eliminate classes of software vulnerability at the processor level.
The funding round was led by Mercia Ventures and PXN Ventures and also included Osney Capital, Black Opal Ventures, and private investors. It follows a £2.5 million investment a year earlier.
Mercia said SCI has fabricated its first devices, secured more than £2 million in orders, and won government contracts worth £7.7 million. It has also entered partnerships with Google Research and Microsoft.
The company describes its ICENI family as the first commercial chips based on CHERI-derived memory-safety technology. Claims that it has produced the world’s first “memory-safe” chip remain company and investor descriptions rather than a neutral industry classification.
The underlying security problem is well established. Memory-safety weaknesses such as buffer overflows, use-after-free conditions, and other improper memory-access bugs account for a large proportion of serious vulnerabilities in software written in languages such as C and C++.
Most efforts to reduce that exposure have focused on safer programming languages, compiler techniques, operating-system mitigations, and software hardening. CHERI — Capability Hardware Enhanced RISC Instructions — introduces another layer by changing how processors represent and enforce access to memory.
Rather than allowing software to treat memory addresses as unrestricted integers, capability-based architectures can attach bounds and permissions to references. The intention is to prevent code from accessing memory outside the region it has legitimately been given, reducing the opportunity for memory corruption to become code execution or privilege escalation.
That approach is particularly relevant to embedded and industrial products, where large C and C++ codebases remain common and where devices may remain deployed for many years. Rewriting mature systems in memory-safe languages is not always commercially or technically realistic, making hardware-enforced protections attractive if they can be adopted without breaking existing development models.
SCI says its chips are designed and packaged in the UK, with fabrication carried out in Germany. The company has also been appointed as a core supplier in the UK government’s Accelerated CHERI Adoption Programme.
The funding arrives as product-security regulation is altering the economics of secure design. The EU Cyber Resilience Act imposes lifecycle security and vulnerability-management obligations on manufacturers of products with digital elements, while government procurement increasingly places security requirements on embedded and critical systems.
Those rules do not mandate a particular processor architecture, but they create a stronger commercial case for technologies that can demonstrate measurable reduction in vulnerability classes. That could make memory safety less of a language or research discussion and more of a procurement consideration.
There are still practical adoption questions. New hardware architectures require toolchains, developer support, testing, operating-system integration, and supply at commercial scale. Customers also need evidence that security benefits survive real product implementation rather than existing only in controlled demonstrations.
SCI’s £5 million round therefore represents more than another semiconductor funding announcement. The company is moving into production at a point when governments and manufacturers are increasingly being asked to reduce vulnerabilities by design. Its next test will be whether hardware-enforced memory safety can move from government-backed research and early orders into repeatable deployment across commercial product lines.
